Job Information
Nvidia Senior High-Performance ASIC Timing Engineer in Santa Clara, California
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.
We are now looking for a motivated to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.
What you'll be doing:
Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs.
Owning static timing analysis and convergence of high-performance designs.
You will be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing methodologies.
Finding the right tradeoffs and balance between power/area/congestions/etc.
What we need to see:
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience in ASIC Design and Timing
Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs.
Strong background and experience in timing constraints generation, clocking, process variations and signal integrity
Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies.
Familiarity with methodology and tools, logic synthesis, equivalence checking.
Strong interpersonal and communication skills and ability to collaborate with cross-functional teams.
Strong understanding of timing and physical design fundamentals
Ways to stand out from the crowd:
Familiarity with high performance mixed-signal designs, and SPICE simulation.
Deep understanding of complex designs and the ability to plan and craft timing critical paths.
Background and expertise in high frequency design closure at subsystem level.
Ability to develop new methodologies/flows as well as workflows to aid timing convergence.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
The base salary range is 136,000 USD - 264,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.