Job Information
Microsoft Corporation Principal PD Engineer in Multiple Locations, India
Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to develop new generation silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking seasoned, passionate, driven and intellectually curious engineers to join our silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, CPU-based custom SOC designs that can perform complex and high-performance functions in the most efficient manner. This team will be involved in numerous projects within Microsoft developing CPU based SOCs silicon for data centers.
We are looking for a Principal Physical Design Engineer to join the team.
Responsibilities
In this high impact role, you will be responsible to:
Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions.
Own partition floorplanning for optimizing blocks for Power, Performance and Area.
Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role.
Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure.
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
Implement robust clock distribution solutions using appropriate methods that meet design requirements.
Additionally drive key pieces of PD implementation methodology or specific areas such as Clocking/Low power optimization/Power & Performance methodology.
Make independent and good technical trade-off decisions between power, area, and timing (PPA).
Be able to guide and coordinate with all sub-partitions PD to be able to take the Sub-chip through PD (construction through signoff) closure.
Partner closely with PD flow/CAD team and PD methodology team.
Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team on all aspects of SC/SS execution, integration & delivery.
Mentor junior engineers on technical issues.
Qualifications
BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
Min 15+ years of experience in semiconductor design.
Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, EMIR closure and physical verification.
Preferred:
Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes.
Technical led PD teams to deliver multiple PD partitions integrated in a subchip/subsystem, having excellent project management skills and ability to juggle multiple projects at once.
Strong understanding of constraints generation, STA, timing optimization, and timing closure.
In-depth understanding of design tradeoffs for power, performance, and area.
Experience in driving PD implementation methodology and/or specific areas such as Clocking/Low power optimization/Power & Performance methodology will be key.
Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
Overall know how of PD-TFM, exposure and some hands-on experience with PD flows bring up/setup/flow flush and PD methodology will be a bonus.
Experience in EDA tools such as Primetime, StarRC, Design Compiler, Fusion Compiler/ICC2, Innovus etc.
Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise.
Strong problem-solving and data analysis skills.
Automation skills using scripting languages such as Perl, TCL, or Python.
Technically leading/guiding a team of multiple PD engineers to deliver a Sub-Chip/SoC will be a big plus.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .