Job Information
IBM BSPDN Integration Engineer in Albany, New York
Introduction
At IBM Research, we invent things that matter to the world. Today, we are pioneering the most promising and disruptive technologies that will transform industries and society, including the future of Hybrid Cloud, AI, and Quantum Computing. We are driven to discover and innovative. With more than 3,000 researchers in 12 labs located across six continents, IBM Research is one of the world’s largest and most influential corporate research labs.
Your role and responsibilities
We are seeking hardware integration engineer with expertise in back side power rail distribution for logic applications. The candidate should have deep expertise in 300mm wafer bonding of Si-CMOS logic devices. The BSPDN integration engineer will be working with a world class team on research and development of the most advanced technology nodes, continuously pushing the boundary of logic technology with partners and clients worldwide.
Required technical and professional expertise
You should have one or more of the following experiences and skills
Experience with 300 mm wafer bonding / Cu interconnect process integration.
Experience with Heterogeneous integration is a plus
High degree of experience in semiconductor device integration, process development: prior experience at a leading a 300mm semiconductor FAB is a plus.
Intermediate level of lithography alignment strategies
Expert level of experience and knowledge of Silicon-CMOS integration: Back End of the Line (BEOL) and middle of line contact modules (MOL)
You must be willing to work in IBM research center in Albany, NY as the primary work location. You must be willing to work an alternate schedule including some evenings/weekend as needed.
Preferred technical and professional experience
A degree in physics, material science/engineering or a related area is required. Bachelors degree with +8 years or Master’s degree with +5 years or Ph.D. with +4 years of silicon semiconductor related experience. Direct multi-skills in Si-CMOS (FEOL, MOL, BEOL, HI, bonding) process development is a plus: